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AC '97 SoundMAX(R) Codec AD1981BL
AC '97 2.3 COMPATIBLE FEATURES
S/PDIF output, 20-bit data format, supporting 48 kHz and 44.1 kHz sample rates Integrated stereo headphone amplifier Variable sample rate audio External audio power-down control >90 dB dynamic range Stereo full-duplex codec 20-bit PCM DAC 3 analog line-level stereo inputs for line-in, AUX, and CD Mono line-level phone input Dual MIC input with built-in programmable preamplifier High quality CD input with ground sense Mono output for speakerphone or internal speaker power management support 48-lead LQFP package, Pb-free available
VREFOUT VREF
ENHANCED FEATURES
Stereo MIC preamplifier support Built-in digital equalizer function for optimized speaker sound Full-duplex variable sample rates from 7040 Hz to 48 kHz with 1 Hz resolution Jack sense pins for automatic output switching Software-programmed VREFOUT output for biasing microphone and external power amplifier Low power 3.3 V operation for analog and digital supplies Multiple codec configuration options
FUNCTIONAL BLOCK DIAGRAM
XTL_OUT XTL_IN SPDIF
AD1981BL
MIC PREAMP MIC1 MIC2 PHONE_IN CD_L CD_GND CD_R AUX_L AUX_R LINE_IN_L LINE_IN_R CD DIFF AMP
MS
G
VOLTAGE REFERENCE CODEC CORE SPDIF TX
G G
2CMIC
PCM L/R ADC RATE
RECORD SELECTOR
PLL
G
M
16-BIT - ADC 16-BIT ADC -
ID0
G
M
ID1
G G MONO_OUT M A
MIX
M M
16-BIT ADC - 16-BIT ADC -
AC '97 INTERFACE
ADC AND DAC SLOT LOGIC
RESET
SYNC
BIT_CLK
EQ CORE STORAGE
M
GA
20-BIT - DAC
BYPASS
SDATA_OUT
EQ
OUTPUT SELECTOR
HP_OUT_L
HP
M
A
M GA GA M M M M GA GA GA GA M M M M M GA GA
GA
20-BIT - DAC PCM FRONT DAC RATE
BYPASS
SDATA_IN
EQ
LINE_OUT_L
MZ
A
G = GAIN A = ATTENUATION M = MUTE Z = HIGH Z
LINE_OUT_R
MZ
A
AC '97 CONTROL REGISTERS
HP_OUT_R
HP
M
A M
ANALOG MIXING CONTROL LOGIC
EAPD
04321-001
JS0
JS1
EAPD
Figure 1. Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD1981BL TABLE OF CONTENTS
Specifications..................................................................................... 3 Test Conditions............................................................................. 3 General Specifications ................................................................. 3 Power-Down States ...................................................................... 5 Timing Parameters ....................................................................... 5 Absolute Maximum Ratings............................................................ 9 Environmental Conditions.......................................................... 9 Pin Configuration and Function Descriptions........................... 10 Indexed Control Registers ............................................................. 12 Control Register Details ................................................................ 13 Reset Register .............................................................................. 13 Master Volume Register............................................................. 13 Headphone Volume Register .................................................... 14 Mono Volume Register .............................................................. 15 Phone Volume Register.............................................................. 15 MIC Volume Register................................................................. 16 Line-In Volume Register............................................................ 16 CD Volume Register................................................................... 17 AUX Volume Register ................................................................ 17 PCM-Out Volume Register....................................................... 18 Record Select Control Register................................................. 19 Record Gain Register ................................................................. 19 General-Purpose Register ......................................................... 20 Power-Down Control/Status Register ..................................... 21 Extended Audio ID Register ..................................................... 22 Extended Audio Status and Control Register......................... 22 PCM Front DAC Rate Register................................................. 23 PCM ADC Rate Register ........................................................... 23 SPDIF Control Register ............................................................. 24 EQ Control Register................................................................... 24 EQ Data Register ........................................................................ 26 Mixer ADC, Input Gain Register ............................................. 26 Jack Sense/Audio Interrupt/Status Register............................ 27 Serial Configuration Register ................................................... 29 Miscellaneous Control Bit Register ......................................... 29 Vendor ID Registers................................................................... 31 Outline Dimensions ....................................................................... 32 Ordering Guide .......................................................................... 32
REVISION HISTORY
1/05--Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Ordering Guide .......................................................... 32 1/04--Revision 0: Initial Version
Rev. A | Page 2 of 32
AD1981BL SPECIFICATIONS
TEST CONDITIONS
Standard test conditions, unless otherwise noted. Table 1.
Parameter Temperature Digital Supply (DVDD) Analog Supply (AVDD) Sample Rate (fS) Input Signal Analog Output Pass Band DAC Test Condition 25C 3.3 V 3.3 V 48 kHz 1008 Hz 20 Hz to 20 kHz Calibrated -3 dB Attenuation Relative to Full Scale 0 dB Input 10 k Output Load (LINE_OUT) 32 Output Load (HP_OUT) Calibrated 0 dB Gain Input -3.0 dB Relative to Full Scale
ADC
GENERAL SPECIFICATIONS
Table 2. Parameter ANALOG INPUT Input Voltage (RMS Values Assume Sine Wave Input) LINE_IN, AUX, CD, PHONE_IN MIC_IN with 20 dB Gain MIC_IN with 0 dB Gain Input Impedance1 Input Capacitance1 MASTER VOLUME Step Size (0 dB to -46.5 dB): LINE_OUT_L, LINE_OUT_R Output Attenuation Range1 Step Size (0 dB to -46.5 dB): MONO_OUT Output Attenuation Range1 Step Size (0 dB to -46.5 dB): HP_OUT_R, HP_OUT_L Output Attenuation Range Span1 Mute Attenuation of 0 dB Fundamental1 PROGRAMMABLE GAIN AMPLIFIER--ADC Step Size (0 dB to 22.5 dB) PGA Gain Range ANALOG MIXER--INPUT GAIN/AMPLIFIERS/ATTENUATORS Signal-to-Noise Ratio (SNR) CD to LINE_OUT Other to LINE_OUT1 Min Typ Max Unit
0.707 2.0 0.0707 0.2 1.707 2.0 20 5 1.5 46.5 1.5 46.5 1.5 46.5 80 1.5 22.5
7.5
V rms V p-p V rms V p-p V rms V p-p k pF dB dB dB dB dB dB dB dB dB
90 90
dB dB
Rev. A | Page 3 of 32
AD1981BL
Parameter Step Size (+12 dB to -34.5 dB) (All Steps Tested): MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC Input Gain/Attenuation Range: MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC DIGITAL DECIMATION AND INTERPOLATION FILTERS1 Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Rejection Group Delay Group Delay Variation over Pass Band ANALOG-TO-DIGITAL CONVERTERS Resolution Total Harmonic Distortion (THD) Dynamic Range (-60 dB Input THD + N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion1CCIF Method) ADC Crosstalk1 Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) Line_In to Other Gain Error2 (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error1 DIGITAL-TO-ANALOG CONVERTERS Resolution Total Harmonic Distortion (THD) LINE_OUT Total Harmonic Distortion (THD) HP_OUT Dynamic Range (-60 dB Input THD + N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion1 (CCIF Method) Gain Error2 (Output FS Voltage Relative to Nominal Output FS Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk1 (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT) ANALOG OUTPUT Full-Scale Output Voltage; LINE_OUT and MONO_OUT Output Impedance1 External Load Impedance1 Output Capacitance1 External Load Capacitance1 Full-Scale Output Voltage; HP_OUT (0 dB Gain) External Load Impedance1 VREF VREFOUT VREFOUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale DAC Output) STATIC DIGITAL SPECIFICATIONS High Level Input Voltage (VIH): Digital Inputs Low Level Input Voltage (VIL) High Level Output Voltage (VOH), IOH = 2 mA
Rev. A | Page 4 of 32
Min
Typ 1.5 46.5
Max
Unit dB dB
0 0.4 x fS 0.6 x fS -74 16/fS 0 16 -87 83 85 -80 -100
0.4 x fS 0.09 0.6 x fS
Hz dB Hz Hz dB sec s Bits dB dB dB dB dB % dB mV Bits dB dB dB dB % dB dB
78
-80 10 0.5 5
82
20 -88 -81 87.5 -100 10 0.7 -80
0.707 2.0 800 10 15 100 1 32 1 1.12 2.25 5 0.65 x DVDD 0.35 x DVDD 0.9 x DVDD 1.225 5
V rms V p-p k pF pF V rms V V mA mV V V V
AD1981BL
Parameter Low Level Output Voltage (VOL), IOL = 2 mA Input Leakage Current Output Leakage Current POWER SUPPLY Power Supply Range (AVDD and DVDD) Power Dissipation Analog Supply Current--3.3 V (AVDD) Digital Supply Current--3.3 V (DVDD) Power Supply Rejection (100 mV p-p Signal at 1 kHz)1 (At Both Analog and Digital Supply Pins, Both ADCs and DACs) CLOCK SPECIFICATIONS1 Input Clock Frequency Recommended Clock Duty Cycle
1 2
Min -10 -10 3.0
Typ
Max 0.1 x DVDD +10 +10 3.47
Unit V A A V mW mA mA dB
2.87 39 48 40
40
24.576 50
60
MHz %
Guaranteed but not tested. Measurements reflect main ADC.
POWER-DOWN STATES
Values presented with VREFOUT not loaded. Table 3.
Parameter Fully Active ADC DAC ADC + DAC Mixer ADC + Mixer DAC + Mixer ADC + DAC + Mixer Standby Headphone Standby Set Bits No Bits Value PR0 PR1 PR1, PR0 PR2 PR2, PR0 PR2, PR1 PR2, PR1, PR0 PR5, PR4, PR3, PR2, PR1, PR0 PR6 DVDD Typ 47.76 40.1 32.8 13.2 47.7 40 32.77 13.9 0 47.7 AVDD Typ 38.9 34.39 26.3 20.55 19.39 14.86 6.39 1.15 0 32 Unit mA mA mA mA mA mA mA mA mA mA
TIMING PARAMETERS
Guaranteed over operating temperature range. Table 4.
Parameter RESET Active Low Pulse Width RESET Inactive to BIT_CLK Start-Up Delay SYNC Active High Pulse Width SYNC Low Pulse Width SYNC Inactive to BIT_CLK Start-Up Delay BIT_CLK Frequency BIT_CLK Frequency Accuracy BIT_CLK Period BIT_CLK Output Jitter1, 2, 3 BIT_CLK High Pulse Width BIT_CLK Low Pulse Width SYNC Frequency
Rev. A | Page 5 of 32
Symbol tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK
Min 162.8
Typ 1.0 1.3 19.5
Max
162.8 12.288 1
tCLK_PERIOD tCLK_HIGH tCLK_LOW 32.56 32.56
81.4 750 42 38 48.0
2000 48.84
Unit ms ns s s ns MHz ppm ns ps ns ns kHz
AD1981BL
Parameter SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) Rising Edge of RESET to High Z Delay Propagation Delay RESET Rise Time Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid Symbol tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF Min 5 5 2 2 2 2 2 2 2 2 0 15 Typ 20.8 2.5 4 4 4 4 4 4 4 4 Max Unit ms ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns
6 6 6 6 6 6 6 6 1.0 25 15 50 15
1 2 3
Guaranteed but not tested. Output jitter is directly dependent on crystal input jitter. Maximum jitter specification is for noncrystal operation only. Crystal operation maximum is much lower.
tRST2CLK tRST_LOW
RESET
tTRI2ACTV
BIT_CLK
tTRI2ACTV
SDATA_IN
Figure 2. Cold Reset Timing (Codec is Supplying the BIT_CLK Signal)
tSYNC_HIGH
SYNC
tSYNC2CLK
BIT_CLK
Figure 3. Warm Reset Timing
Rev. A | Page 6 of 32
04321-003
04321-002
AD1981BL
tCLK_LOW
BIT_CLK
tCLK_HIGH tCLK_PERIOD tSYNC_LOW
SYNC
04321-004
tSYNC_HIGH tSYNC_PERIOD
Figure 4. Clock Timing
BIT_CLK
tRISECLK
tFALLCLK
SYNC
tRISESYNC
tFALLSYNC
SDATA_IN
tRISEDIN
tFALLDIN
SDATA_OUT
tRISEDOUT
tFALLDOUT
Figure 5. Signal Rise and Fall Times
SLOT 1 SYNC
SLOT 2
BIT_CLK
SDATA_OUT
WRITE TO 0x20
DATA PR4
tS2_PDOWN
SDATA_IN BIT_CLK NOT TO SCALE
04321-006
Figure 6. AC-Link Low Power Mode Timing
Rev. A | Page 7 of 32
04321-005
AD1981BL
tCO tSETUP
BIT_CLK
VIH
VIL
SDATA_OUT SDATA_IN SYNC VOH VOL
04321-007
tHOLD
Figure 7. AC-Link Low Power Mode Timing, SYNC and BIT_CLK Chopped
RESET
SDATA_OUT
tSETUP2RST
04321-008
SDATA_IN, BIT_CLK, EAPD, SPDIF_OUT AND DIGITAL I/O
HIGH Z
tOFF
Figure 8. ATE Test Mode
Rev. A | Page 8 of 32
AD1981BL ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 5.
Parameter Power Supplies Digital (DVDD) Analog (AVDD) Input Current (Except Supply Pins) Signals Pins Digital Input Voltage Analog Input Voltage Ambient Temperature Range (Operating) Rating -0.3 V to +3.6 V -0.3 V to +6.0 V 10 mA -0.3 V to DVDD + 0.3 V -0.3 V to AVDD + 0.3 V 0C to 70C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating (LQFP Package) TCASE = Case Temperature in C PD = Power Dissipation in W JA Thermal Resistance (Junction to Ambient) JC Thermal Resistance (Junction to Case) Table 6. Thermal Resistance
Package LQFP JA 50.1C/W JC 17.8C/W
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 9 of 32
AD1981BL PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
HP_OUT_L AVDD3 AVSS3 SPDIF EAPD ID1 ID0 AVDD2
38
48
47
46
45
44
43
42
41
40
39
37
DVDD1 1 XTL_IN 2 XTL_OUT 3 DVSS1 4 SDATA_OUT 5 BIT_CLK 6 DVSS2 7 SDATA_IN 8 DVDD2 9 SYNC 10 RESET 11 NC 12
13 14 15 16 17 18 19 20 21 22 23 24
MONO_OUT
36 LINE_OUT_R 35 LINE_OUT_L 34 AVDD4 33 AVSS4 32 AFILT4 31 AFILT3 30 AFILT2 29 AFILT1 28 VREFOUT 27 VREF 26 AVSS1 25 AVDD1
HP_OUT_R
AD1981BL
TOP VIEW (Not to Scale)
PHONE_IN
AVSS2
NC
CD_GND_REF
LINE_IN_R
LINE_IN_L
JS1
AUX_R
JS0
AUX_L
CD_R
CD_L
MIC1
MIC2
NC = NO CONNECT
Figure 9. 48-Lead LQFP Pin Configuration
Table 7. Pin Function Descriptions
Pin No. DIGITAL I/O 2 3 5 6 8 10 11 48 CHIP SELECTS1 45 46 JACK SENSE AND EAPD 17 16 47 ANALOG I/O 13 14 15 18 19 20 21 Mnemonic XTL_IN XTL_OUT SDATA_OUT BIT_CLK SDATA_IN SYNC RESET SPDIF ID0 ID1 JS0 JS1 EAPD PHONE_IN AUX_L AUX_R CD_L CD_GND_REF CD_ R MIC1 I/O I O I O/I O I I O I I I I O I I I I I I I Description Crystal Input (24.576 MHz) or External Clock Input. Crystal Output. AC-Link Serial Data Output, AD1981BL Data Input Stream. AC-Link Bit Clock Output (12.288 MHz) or Bit Clock Input, if Secondary Mode Selected. AC-Link Serial Data Input, AD1981BL Data Output Stream. AC-Link Frame Sync. AC-Link Reset, AD1981BL Master Hardware Reset. S/PDIF Output. Chip Select Input 0 (Active Low). This pin can also be used as the chain input from a secondary codec. Chip Select Input 1 (Active Low). Jack Sense 0 Input. Jack Sense 1 Input. External Amp Power-Down Control. Phone Input. Mono input from telephony subsystem speaker phone or handset. Auxiliary Input Left Channel. Auxiliary Input Right Channel. CD Audio Left Channel. CD Audio Analog Ground Reference for Differential CD Input. CD Audio Right Channel. Microphone 1 Input (Mono) or Left Channel when 2-Channel Mode Selected (Stereo MIC).
Rev. A | Page 10 of 32
04321-009
AD1981BL
Pin No. 22 23 24 35 36 37 39 41 FILTER/REFERENCE2 27 28 29 30 31 32 POWER AND GROUND SIGNALS 1 4 7 9 25 26 38 40 43 44 34 33 NO CONNECTS 12 42 Mnemonic MIC2 LINE_IN_L LINE_IN_R LINE_OUT_L LINE_OUT_R MONO_OUT HP_OUT_L HP_OUT_R VREF VREFOUT AFILT1 AFILT2 AFILT3 AFILT4 I/O I I I O O O O O O O O O O O Description Microphone 2 Input (Mono) or Right Channel when 2-Channel Mode Selected (Stereo MIC). Line-In Left Channel. Line-In Right Channel. Line-Out (Front) Left Channel. Line-Out (Front) Right Channel. Monaural Output to Telephony Subsystem Speaker Phone. Headphone Left-Channel Output. Headphone Right-Channel Output. Voltage Reference Filter. Voltage Reference Output 5 mA Drive (Intended for MIC Bias and Power Amp Bias). Antialiasing Filter Capacitor--ADC Right Channel. Antialiasing Filter Capacitor--ADC Left Channel. Antialiasing Filter Capacitor--Mixer ADC Right Channel. Antialiasing Filter Capacitor--Mixer ADC Left Channel.
DVDD1 DVSS1 DVSS2 DVDD2 AVDD1 AVSS1 AVDD2 AVSS2 AVDD3 AVSS3 AVDD4 AVSS4 NC NC
I I I I I I I I I I I I
Digital VDD, 3.3 V. Digital GND. Digital GND. Digital VDD, 3.3 V. Analog VDD, 3.3 V. Analog GND. Analog VDD, 3.3 V. Analog GND. Analog VDD, 3.3 V. Analog GND. Analog VDD, 3.3 V. Analog GND. No Connect. No Connect.
1 2
These pins can also be used to select an external clock. See Table 44. These signals are connected to resistors, capacitors, or specific voltages.
Rev. A | Page 11 of 32
AD1981BL INDEXED CONTROL REGISTERS
Table 8.
Reg 0x00 0x02 0x04 0x06 0x0C 0x0E 0x10 0x12 0x16 0x18 0x1A 0x1C 0x20 0x26 0x28 0x2A 0x2C 0x32 0x3A 0x60 0x62 0x64 0x72 0x74 0x76 0x7C 0x7E Name Reset Master Volume Headphone Volume Mono Volume Phone Volume MIC Volume Line-In Volume CD Volume AUX Volume PCM-Out Volume Record Select Record Gain GeneralPurpose Power-Down Ctrl/Stat Ext'd Audio ID Ext'd Audio Stat/Ctrl PCM Front DAC Rate PCM L/R ADC Rate SPDIF Control EQ Ctrl EQ Data Mixer ADC, Volume Jack Sense Serial Config Misc Control Bit Vendor ID1 Vendor ID2 D15 X MM HPM MVM PHM MCM LVM CVM AM OM X IM X EAPD IDC1 VFORCE SRF15 SRA15 V EQM CFD15 MXM X SLOT 16 DACZ F7 T7 D14 SE4 X X X X X X X X X X X X PR6 IDC0 X SRF14 SRA14 X MAD LBEN CFD14 X X REGM 2 X F6 T6 D13 SE3 X X X X X X X X X X X X PR5 X X SRF13 SRA13 SPSR1 X CFD13 X X REGM 1 MSPLT F5 T5 D12 SE2 LMV4 LHV4 X X X LLV4 LCV4 LAV4 LOV4 X X X PR4 X X SRF12 SRA12 SPSR0 X CFD12 X JS MT2 REGM 0 LODIS F4 T4 D11 SE1 LMV3 LHV3 X X X LLV3 LCV3 LAV3 LOV3 X LIM3 X PR3 REVC1 X SRF11 SRA11 L X CFD11 LMG3 JS MT1 X DAM F3 T3 D10 SE0 LMV2 LHV2 X X X LLV2 LCV2 LAV2 LOV2 LS2 LIM2 X PR2 REVC0 SPCV SRF10 SRA10 CC6 X CFD10 LMG2 JS MT0 X X F2 T2 D9 ID9 LMV1 LHV1 X X X LLV1 LCV1 LAV1 LOV1 LS1 LIM1 MIX PR1 AMAP X SRF9 SRA9 CC5 X CFD9 LMG1 JS1 EQB X FMXE F1 T1 D8 ID8 LMV0 LHV0 X X X LLV0 LCV0 LAV0 LOV0 LS0 LIM0 MS PR0 X X SRF8 SRA8 CC4 X CFD8 LMG0 JS0 EQB CHEN X F0 T0 D7 ID7 RM1 RM1 X X X RM1 RM1 RM1 RM1 X RM
1
D6 ID6 X X X X M20 X X X X X X X X X X SRF6 SRA6 CC2 CHS CFD6 X JS0 TMR X 2CMIC S6 REV6
D5 ID5 X X X X X X X X X X X X X DSA1 SPSA1 SRF5 SRA5 CC1 BCA5 CFD5 X JS1 MD X X S5 REV5
D4 ID4 RMV4 RHV4 MV4 PHV4 MCV4 RLV4 RCV4 RAV4 ROV4 X X X X DSA0 SPSA0 SRF4 SRA4 CC0 BCA4 CFD4 X JS0 MD INTS MAD ST S4 REV4
D3 ID3 RMV3 RHV3 MV3 PHV3 MCV3 RLV3 RCV3 RAV3 ROV3 X RIM3 X REF X X SRF3 SRA3 PRE BCA3 CFD3 RMG3 JS1 ST X VREFH S3 REV3
D2 ID2 RMV2 RHV2 MV2 PHV2 MCV2 RLV2 RCV2 RAV2 ROV2 RS2 RIM2 X ANL SPDIF SPDIF SRF2 SRA2 COPY BCA2 CFD2 RMG2 JS0 ST SPAL VREFD S2 REV2
D1 ID1 RMV1 RHV1 MV1 PHV1 MCV1 RLV1 RCV1 RAV1 ROV1 RS1 RIM1 X DAC X X SRF1 SRA1 /AUD BCA1 CFD1 RMG1 JS1 INT SPDZ MBG1 S1 REV1
D0 ID0 RMV0 RHV0 MV0 PHV0 MCV0 RLV0 RCV0 RAV0 ROV0 RS0 RIM0 X ADC VRAS VRA SRF0 SRA0 PRO BCA0 CFD0 RMG0 JS0 INT SPLNK MBG0 S0 REV0
Default 0x0090 0x8000 0x8000 0x8000 0x8008 0x8008 0x8808 0x8808 0x8808 0x8808 0x0000 0x8000 0x0000 0x000X 0xX605 0x0000 0xBB80 0xBB80 0x2000 0x8080 0x0000 0x8000 0x0000 0x7001 0x0000 0x4144 0x5374
LPBK X X X SRF7 SRA7 CC3 SYM CFD7 RM1 JS1 TMR X MAD PD S7 REV7
All registers are not shown. Bits containing an X are assumed to be reserved. Odd register addresses are aliased to the next lower even address. Reserved registers should not be written. Zeros should be written to reserved bits.
1
For AC `97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect.
Rev. A | Page 12 of 32
AD1981BL CONTROL REGISTER DETAILS
RESET REGISTER
Index 0x00
Reg No. 0x00 Name Reset D15 X D14 SE4 D13 SE3 D12 SE2 D11 SE1 D10 SE0 D9 ID9 D8 ID8 D7 ID7 D6 ID6 D5 ID5 D4 ID4 D3 ID3 D2 ID2 D1 ID1 D0 ID0 Default 0x0090
X is a wild card, and has no effect on the value. Writing any value to this register performs a register reset that causes all registers to revert to their default values (except 0x74, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.
ID[9:0] Identify Capability. The ID decodes the capabilities of AD1981BL based on the functions listed in Table 9.
Table 9. ID Bits
Bit ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 Function Dedicated MIC PCM in Channel Modem Line Codec Support Bass and Treble Control Simulated Stereo (Mono to Stereo) Headphone Out Support Loudness (Bass Boost) Support 18-Bit DAC Resolution 20-Bit DAC Resolution 18-Bit ADC Resolution 20-Bit ADC Resolution AD1981B 0 0 0 0 1 0 0 1 0 0
MASTER VOLUME REGISTER
Index 0x02
This register controls the Line_Out volume controls for both stereo channels and the mute bit. Each volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC '97 defines 6-bit volume registers, to maintain compatibility whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits read 1s whenever these bits are set to 1. Refer to Table 12 for examples.
Reg No. 0x02 Name Master Volume D15 MM D14 X D13 X D12 LMV4 D11 LMV3 D10 LMV2 D9 LMV1 D8 LMV0 D7 RM1 D6 X D5 X D4 RMV4 D3 RMV3 D2 RMV2 D1 RMV1 D0 RMV0 Default 0x8000
1
For AC `97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved.
Table 10.
Bit RMV [4:0] RM LMV [4:0] MM Mnemonic Right Master Volume Control Right-Channel Mute Left Master Volume Control Master Volume Mute Function The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the MM bit. Otherwise, this bit always reads 0 and has no effect when set to 1. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
Rev. A | Page 13 of 32
AD1981BL
HEADPHONE VOLUME REGISTER
Index 0x04
This register controls the headphone volume controls for both stereo channels and the mute bit. Each volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC '97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits read 1s whenever these bits are set to 1. Refer to Table 12 for examples.
Reg No. 0x04
Name Headphone Volume
D15 HPM
D14 X
D13 X
D12 LHV4
D11 LHV3
D10 LHV2
D9 LHV1
D8 LHV0
D7 RM1
D6 X
D5 X
D4 RHV4
D3 RHV3
D2 RHV2
D1 RHV1
D0 RHV0
Default 0x8000
1
For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved.
Table 11.
Bit RHV [4:0] RM LHV [4:0] HPM Mnemonic Right Headphone Volume Control Right-Channel Mute Left Headphone Volume Control Headphone Volume Mute Function The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the HPM bit. Otherwise, this bit always reads 0 and has no effect when set to 1. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
Table 12. Volume Settings for Master and Headphone
Reg. 0x76 MSPLT1 0 0 0 0 0 1 1 1 D15 0 0 0 0 1 0 1 1 Write 00 0000 00 1111 01 1111 1X XXXX XX XXXX 1X XXXX XX XXXX XX XXXX Control Bits Master Volume (0x02) and Headphone Volume (0x04) Left-Channel Volume D [13:8] Right-Channel Volume D [5:0] Readback Function Write Readback Function D71 00 0000 00 1111 01 1111 01 1111 XX XXXX 01 1111 XX XXXX XX XXXX 0 dB Gain -22.5 dB Gain -46.5 dB Gain -46.5 dB Gain - dB Gain, Muted -46.5 dB Gain - dB Gain, Left Only Muted - dB Gain, Left Muted X X X X X 1 0 1 00 0000 00 1111 01 1111 1X XXXX XX XXXX XX XXXX XX XXXX XX XXXX 00 0000 00 1111 01 1111 01 1111 XX XXXX XX XXXX XX XXXX XX XXXX 0 dB Gain -22.5 dB Gain -46.5 dB Gain -46.5 dB Gain - dB Gain, Muted - dB Gain, Right Only Muted -46.5 dB Gain - dB Gain, Right Muted
1
For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. X is a wild card, and has no effect on the value.
Rev. A | Page 14 of 32
AD1981BL
MONO VOLUME REGISTER
Index 0x06
This register controls the mono output volume and mute bit. The volume register contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC '97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 bit is set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits read 1s whenever this bit is set to 1. Refer to Table 14 for examples.
Reg No. 0x06 Name Mono Volume D15 MVM D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 X D4 MV4 D3 MV3 D2 MV2 D1 MV1 D0 MV0 Default 0x8000
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 13.
Bit MV [4:0] MVM Mnemonic Mono Volume Control Mono Volume Mute Function The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. When this bit is set to 1, the channel is muted.
Table 14. Volume Settings for Mono
D15 0 0 0 1 Write 0 0000 0 1111 1 1111 X XXXX Control Bits D [4:0] for Mono (0x06) Readback 0 0000 0 1111 1 1111 X XXXX Function 0 dB Gain -22.5 dB Gain -46.5 dB Gain - dB Gain, Muted
An X is a wild card, and has no effect on the value.
PHONE VOLUME REGISTER
Index 0x0C
Reg No. 0x0C Name Phone Volume D15 PHM D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 X D4 PHV4 D3 PHV3 D2 PHV2 D1 PHV1 D0 PHV0 Default 0x8008
All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 17 for examples.
Table 15.
Bit PHV [4:0] Mnemonic Phone Volume Function Allows setting the phone volume attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, with the mute bit enabled. When this bit is set to 1, the phone channel is muted.
PHM
Phone Mute
All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 17 for examples.
Rev. A | Page 15 of 32
AD1981BL
MIC VOLUME REGISTER
Index 0x0E
Reg No. 0x0E Name MIC Volume D15 MCM D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 M20 D5 X D4 MCV4 D3 MCV3 D2 MCV2 D1 MCV1 D0 MCV0 Default 0x8008
All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 17 for examples.
Table 16.
Bit MCV [4:0] Mnemonic MIC Volume Gain Function Allows setting the phone volume attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, with the mute bit enabled. This bit allows setting additional MIC gain to increase the microphone sensitivity. The nominal gain boost by default is 20 dB; however, Bits D0 and D1 (MBG [1:0]) on the miscellaneous control bits register (0x76) allow changing the gain boost to 10 dB or 30 dB, if necessary. 0 = Disabled; Gain = 0 dB 1 = Enabled; Default Gain = 20 dB (see Register 0x76, Bits D0, D1) When this bit is set to 1, the MIC channel is muted.
M20
MIC Gain Boost
MCM
MIC Mute
Table 17. Volume Settings for Phone and MIC
D15 0 0 0 1 Write 0 0000 0 1000 1 1111 X XXXX Control Bits D [4:0] Phone (0x0C) and MIC (0x0E) Readback 0 0000 0 1000 1 1111 X XXXX Function 12 dB Gain 0 dB Gain -34.5 dB Gain - db Gain, Muted
X is a wild card, and has no effect on the value.
LINE-IN VOLUME REGISTER
Index 0x10
Reg No. 0x10 Name Line-In Volume D15 LVM D14 X D13 X D12 LLV4 D11 LLV3 D10 LLV2 D9 LLV1 D8 LLV0 D7 RM1 D6 X D5 X D4 RLV4 D3 RLV3 D2 RLV2 D1 RLV1 D0 RLV0 Default 0x8808
1
For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 22 for examples.
Table 18.
Bit RLV [4:0] RM LLV [4:0] LVM Mnemonic Line-In Volume Right Right-Channel Mute Line-In Volume Left Line-In Mute Function Allows setting the line-in right-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the LM bit. Otherwise, this bit always reads 0 and has no effect when set to 1. Allows setting the line-in left-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
Rev. A | Page 16 of 32
AD1981BL
CD VOLUME REGISTER
Index 0x12
Reg No. 0x12 Name CD Volume D15 CVM D14 X D13 X D12 LCV4 D11 LCV3 D10 LCV2 D9 LCV1 D8 LCV0 D7 RM1 D6 X D5 X D4 RCV4 D3 RCV3 D2 RCV2 D1 RCV1 D0 RCV0 Default 0x8808
1
For AC `97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 22 for examples.
Table 19.
Bit RCV [4:0] RM LCV [4:0] CVM Mnemonic Right CD Volume Right-Channel Mute Left CD Volume CD Volume Mute Function Allows setting the CD right-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the CVM bit. Otherwise, this bit always reads 0 and has no affect when set to 1. Allows setting the CD left-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
AUX VOLUME REGISTER
Index 0x16
Reg No. 0x16 Name AUX Volume D15 AM D14 X D13 X D12 LAV4 D11 LAV3 D1 LAV2 D9 LAV1 D8 LAV0 D7 RM1 D6 X D5 X D4 RAV4 D3 RAV3 D2 RAV2 D1 RAV1 D0 RAV0 Default 0x8808
1
For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 22 for examples.
Table 20.
Bit RAV [4:0] RM LAV [4:0] AM Mnemonic Right AUX Volume Right-Channel Mute Left AUX Volume AUX Volume Mute Function Allows setting the AUX right-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the AM bit. Otherwise, this bit always reads 0 and has no affect when set to 1. Allows setting the AUX left-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
Rev. A | Page 17 of 32
AD1981BL
PCM-OUT VOLUME REGISTER
Index 0x18
Reg No. 0x18 Name PCM-Out Volume D15 OM D14 X D13 X D12 LOV4 D11 LOV3 D10 LOV2 D9 LOV1 D8 LOV0 D7 RM1 D6 X D5 X D4 ROV4 D3 ROV3 D2 ROV2 D1 ROV1 D0 ROV0 Default 0x8808
1
For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 22 for examples.
Table 21.
Bit ROV [4:0] RM LOV [4:0] OM Mnemonic Right PCM-Out Volume Right-Channel Mute Left PCM-Out Volume PCM-Out Volume Mute Function Allows setting the PCM right-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the OM bit. Otherwise, this bit always reads 0 and has no effect when set to 1. Allows setting the PCM left-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. When this bit is set to 1, both the left and right channels are muted unless the MSPLT bit in Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
Table 22. Volume Settings for Line-In, CD Volume, AUX, and PCM-Out
Reg. 0x76 MSPLT1 0 0 0 0 1 D15 0 0 0 1 0 Control Bits Line-In (0x10), CD (0x12), AUX (0x16), and PCM-Out (0x18) Left-Channel Volume D [12:8] Right-Channel Volume D [4:0] 1 Write Readback Function D7 Write Readback 0 0000 0 0000 12 dB Gain X 0 0000 0 0000 0 1000 0 1000 0 dB Gain X 0 1000 0 1000 1 1111 1 1111 X 1 1111 1 1111 +34.5 dB Gain X XXXX X XXXX X X XXXX X XXXX - dB Gain, Muted 1 1111 1 1111 1 X XXXX X XXXX -34.5 dB Gain X XXXX X XXXX - dB Gain, Left Only Muted - dB Gain, Left Muted 0 1 1111 1 1111
1
1
Function 12 dB Gain 0 dB Gain -34.5 dB Gain - dB Gain, Muted - dB Gain, Right Only Muted -34.5 dB Gain - dB Gain, Right Muted
1
1
X XXXX
X XXXX
1
X XXXX
X XXXX
1
For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. X is a wild card, and has no effect on the value.
Rev. A | Page 18 of 32
AD1981BL
RECORD SELECT CONTROL REGISTER
Index 0x1A
Reg No. 0x1A Name Record Select D15 X D14 X D13 X D12 X D11 X D10 LS2 D9 LS1 D8 LS0 D7 X D6 X D5 X D4 X D3 X D2 RS2 D1 RS1 D0 RS0 Default 0x0000
Used to select the record source independently for right and left. The default value is 0x0000, which corresponds to MIC In. Refer to Table 24 for examples. All registers are not shown, and bits containing an X are assumed to be reserved.
Table 23.
Bit RS [2:0] LS [2:0] Function Right Record Select Left Record Select
Table 24. Settings for Record Select Control
LS [10:8] 000 001 010 011 100 101 110 111 Left Record Source MIC CD_L Muted AUX_L LINE_IN_L Stereo Mix (L) Mono Mix PHONE_IN RS [2:0] 000 001 010 011 100 101 110 111 Right Record Source MIC CD_R Muted AUX_R LINE_IN_R Stereo Mix (R) Mono Mix PHONE_IN
RECORD GAIN REGISTER
Index 0x1C
Reg No. 0x1C Name Record Gain D15 IM D14 X D13 X D12 X D11 LIM3 D10 LIM2 D9 LIM1 D8 LIM0 D7 RM1 D6 X D5 X D4 X D3 RIM3 D2 RIM2 D1 RIM1 D0 RIM0 Default 0x8000
1
For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 24 for examples.
Table 25.
Bit RIM [3:0] RM LIM [3:0] IM Mnemonic Right Input Mixer Gain Control Right-Channel Mute Left Input Mixer Gain Control Input Mute Function Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB. Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the IM bit. Otherwise, this bit always reads 0 and has no affect when set to 1. Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
Rev. A | Page 19 of 32
AD1981BL
Table 26. Settings for Record Gain Register
Reg. 0x76 MSPLT1 0 0 0 1 D15 0 0 1 0 Control Bits Record Gain (1Channel) Left-Channel Input Mixer D [11:8] Right-Channel Input Mixer D [3:0] Write Readback Function Write Readback Function D71 1111 1111 22.5 dB Gain X 1111 1111 22.5 dB Gain 0000 0000 0 dB Gain X 0000 0000 0 dB Gain XXXX XXXX X XXXX XXXX - dB Gain, - dB Gain, Muted Muted 1111 1111 22.5 dB Gain 1 XXXX XXXX - dB Gain, Right Only Muted XXXX XXXX 0 1111 1111 22.5 dB Gain - dB Gain, Left Only Muted XXXX XXXX 1 XXXX XXXX - dB Gain, - dB Gain, Left Muted Right Muted
1
1
1
1
1
For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. X is a wild card, and has no effect on the value.
GENERAL-PURPOSE REGISTER
Index 0x20
Reg No. 0x20 Name General-Purpose D15 X D14 X D13 X D12 X D11 X D10 X D9 MIX D8 MS D7 LPBK D6 X D5 X D4 X D3 X D2 X D1 X D0 X Default 0x0000
This register should be read before writing to generate a mask for only the bit(s) that need to be changed. All registers are not shown, and bits containing an X are assumed to be reserved.
Table 27.
Bit LPBK Mnemonic Loopback Control Function ADC/DAC Digital Loopback Mode. 0 = No Loopback (default). 1 = Loopback PCM Digital Data from ADC Output to DAC. Selects mono MIC input. 0 = Select MIC1. 1 = Select MIC2. See the 2CMIC bit in Register 0x76 to enable stereo microphone recording. Selects mono output audio source. 0 = Mixer Mono Output (reset default). 1 = MIC1 Channel.
MS
MIC Select
MIX
Mono Output Select
Rev. A | Page 20 of 32
AD1981BL
POWER-DOWN CONTROL/STATUS REGISTER
Index 0x26
Reg No. 0x26 Name Power-Down Ctrl/Stat D15 EAPD D14 PR6 D13 PR5 D12 PR4 D11 PR3 D10 PR2 D9 PR1 D8 PR0 D7 X D6 X D5 X D4 X D3 REF D2 ANL D1 DAC D0 ADC Default 0x000X
The ready bits are read-only; writing to REF, ANL, DAC, ADC has no effect. These bits indicate the status for the AD1981BL subsections. If the bit is a 1, that subsection is ready. Ready is defined as the subsection able to perform in its nominal state. All registers are not shown, and bits containing an X are assumed to be reserved.
Table 28.
Bit ADC DAC ANL REF PR [6:0] Mnemonic Function ADC Sections Ready to Transmit Data. DAC Sections Ready to Accept Data. Analog Amplifiers, Attenuators, and Mixers Ready. Voltage References, VREF and VREFOUT, Up to Nominal Level. The first three bits are to be used individually rather than in combination with each other. PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until the reference is powered up. PR5 has no effect unless all ADCs, DACs, and the ac-link are powered down. The reference and the mixer can be either powered up or powered down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are both set. In multiple codec systems, the master codec's PR5 and PR4 bits control the slave codec. PR5 is also effective in the slave codec, if the master's PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5. Controls the state of the EAPD pin. EAPD = 0 sets the EAPD pin low, enabling an external power amplifier (reset default). EAPD = 1 sets the EAPD pin high, shutting the external power amplifier off.
Codec PowerDown Modes
EAPD
External Audio Power-Down Control
Table 29.
Power-Down State ADCs and Input MUX Power-Down DACs Power-Down Analog Mixer Power-Down (VREF and VREFOUT On) Analog Mixer Power-Down (VREF and VREFOUT Off) AC-Link Interface Power-Down Internal Clocks Disabled ADC and DAC Power-Down VREF Standby Mode Total Power-Down Headphone Amp Power-In Standby Set Bits PR0 PR1 PR1, PR2 PR0, PR1, PR3 PR4 PR0, PR1, PR4, PR5 PR0, PR1 PR0, PR1, PR2, PR4, PR5 PR0, PR1, PR2, PR3, PR4, PR5, PR6 PR6 PR [6:0] [000 0001] [000 0010] [000 0101] [000 1011] [001 0000] [011 0011] [000 0011] [011 0111] [111 1111] [100 0000]
Rev. A | Page 21 of 32
AD1981BL
EXTENDED AUDIO ID REGISTER
Index 0x28
Reg No. 0x28 Name Ext'd Audio ID D15 IDC1 D14 IDC0 D13 X D12 X D11 REVC1 D10 REVC0 D9 AMAP D8 X D7 X D6 X D5 DSA1 D4 DSA0 D3 X D2 SPDIF D1 X D0 VRAS Default 0xX605
The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates that one or more of the extended audio features are supported. All registers are not shown, and bits containing an X are assumed to be reserved.
Table 30.
Bit VRAS SPDIF Mnemonic Variable Rate PCM Audio Support (Read-Only) SPDIF Support (Read-Only) Function This bit returns a 1 when Read To indicates that the variable rate PCM audio is supported. This bit returns a 1 when Read To indicates that the SPDIF transmitter is supported (IEC958). This bit is also used to validate that the SPDIF transmitter output is enabled. The SPDIF bit can be set high only if the SPDIF pin (Pin 48) is pulled down at power-up, enabling the codec transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled; therefore, this bit returns a low, indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF transmitter is actually enabled. Reset default = 00. 00 DACs 1, 2 = 3 and 4. 01 DACs 1, 2 = 7 and 8. 10 DACs 1, 2 = 6 and 9. 11 Reserved. This bit returns a 1 when read to indicate that slot/DAC mappings based on the codec ID are supported. REVC [1:0] = 01 indicates that the codec is AC '97 revision 2.2-compliant (read-only). 00 = Primary. 01, 10, 11 = Secondary.
DSA [1:0]
DAC Slot Assignments (Read/Write)
AMAP REVC [1:0] IDC [1:0]
Slot DAC Mappings Based on Codec ID (Read-Only) AC '97 Revision Compliance Indicates Codec Configuration (Read-Only)
EXTENDED AUDIO STATUS AND CONTROL REGISTER
Index 0x2A
Reg No. 0x2A Name Ext'd Audio Stat/Ctrl D15 VFORCE D14 X D13 X D12 X D11 X D10 SPCV D9 X D8 X D7 X D6 X D5 SPSA1 D4 SPSA0 D3 X D2 SPDIF D1 X D0 VRA Default 0x0000
The extended audio status and control register is a read/write register that provides status and control of the extended audio features. All registers are not shown, and bits containing an X are assumed to be reserved.
Table 31.
Bit VRA Mnemonic Variable Rate Audio (Read/Write) SPDIF Transmitter Subsystem Enable/Disable Bit (Read/Write) Function VRA = 0 sets the fixed sample rate audio to 48 kHz (reset default). VRA = 1 enables variable rate audio mode (enables sample rate registers and SLOTREQ signaling). SPDIF = 1 enables the SPDIF transmitter. SPDIF = 0 disables the SPDIF transmitter (default). This bit is also used to validate that the SPDIF transmitter output is enabled. The SPDIF bit can be set high only if the SPDIF pin (Pin 48) is pulled down at power-up, enabling the codec transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled and this bit returns a low, indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF transmitter is enabled. These bits control the SPDIF slot assignment and respective defaults, depending on the codec ID configuration.
Rev. A | Page 22 of 32
SPDIF
SPSA [1:0]
SPDIF Slot Assignment Bits (Read/Write)
AD1981BL
Bit SPCV Mnemonic SPDIF Configuration Valid (Read-Only) Function This bit indicates the status of the SPDIF transmitter subsystem, enabling the driver to determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent of the SPDIF enable bit status. SPCV = 0 indicates that the current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not valid (not supported). SPCV = 1 indicates that the current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid (supported). When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R subframe) to be controlled by the V bit (D15) in Register 0x3A (SPDIF control register). VFORCE = 0 and V = 0; the validity bit is managed by the codec error detection logic. VFORCE = 0 and V = 1; the validity bit is forced high, indicating the subframe data is invalid. VFORCE = 1 and V = 0; the validity bit is forced low, indicating the subframe data is valid. VFORCE = 1 and V = 1; the validity bit is forced high, indicating the subframe data is invalid.
VFORCE
Validity Force Bit (Reset Default = 0)
Table 32. AC '97 2.2 AMAP-Compliant Default SPDIF Slot Assignments
Codec ID 00 00 00 01 01 10 10 11 Function 2-Channel Primary w/SPDIF 4-Channel Primary w/SPDIF 6-Channel Primary w/SPDIF +2-Channel Secondary w/SPDIF +4-Channel Secondary w/SPDIF +2-Channel Secondary w/SPDIF +4-Channel Secondary w/SPDIF +2-Channel Secondary w/SPDIF SPSA = 00 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 SPSA = 01 7 and 8 (default) 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 SPSA = 10 6 and 9 6 and 9 (default) 6 and 9 6 and 9 (default) 6 and 9 6 and 9 (default) 6 and 9 6 and 9 SPSA = 11 10 and 11 10 and 11 10 and 11 (default) 10 and 11 (default) 10 and 11 (default) 10 and 11 (default)
PCM FRONT DAC RATE REGISTER
Index 0x2C
Reg No. 0x2C Name PCM Front DAC Rate D15 SRF15 D14 SRF14 D13 SRF13 D12 SRF12 D11 SRF11 D10 SRF10 D9 SRF9 D8 SRF8 D7 SRF7 D6 SRF6 D5 SRF5 D4 SRF4 D3 SRF3 D2 SRF2 D1 SRF1 D0 SRF0 Default 0xBB80
This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz.
Table 33.
Bit SRF [15:0] Mnemonic Sample Rate Function The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to VRA, the sample rate is reset to 48 kHz.
PCM ADC RATE REGISTER
Index 0x32
Reg No. 0x32 Name PCM L/R ADC Rate D15 SRA15 D14 SRA14 D13 SRA13 D12 SRA12 D11 SRA11 D10 SRA10 D9 SRA9 D8 SRA8 D7 SRA7 D6 SRA6 D5 SRA5 D4 SRA4 D3 SRA3 D2 SRA2 D1 SRA1 D0 SRA0 Default 0xBB80
This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz.
Table 34.
Bit SRA [15:0] Mnemonic Sample Rate Function The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to VRA, the sample rate is reset to 48 kHz.
Rev. A | Page 23 of 32
AD1981BL
SPDIF CONTROL REGISTER
Index 0x3A
Reg No. 0x3A Name SPDIF Control D15 V D14 X D13 SPSR1 D12 SPSR0 D11 L D10 CC6 D9 CC5 D8 CC4 D7 CC3 D6 CC2 D5 CC1 D4 CC0 D3 PRE D2 COPY D1 AUD D0 PRO Default 0x2000
Register 0x3A is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the exception of V, this register should be written to only when the SPDIF transmitter is disabled (SPDIF bit in Register 0x2A is 0). This ensures that control and status information start up correctly at the beginning of SPDIF transmission.
Table 35.
Bit PRO AUD COPY PRE CC [6:0] L SPSR [1:0] Mnemonic Professional Nonaudio Copyright Pre-emphasis Category Code Generation Level SPDIF Transmit Sample Rate Function 1 = Professional use of channel status. 0 = Consumer. 1 = Data is non-PCM format. 0 = Data is PCM format. 1 = Copyright is asserted. 0 = Copyright is not asserted. 1 = Filter pre-emphasis is 50 s/15 s. 0 = Pre-emphasis is none. Programmed according to IEC standards, or as appropriate. Programmed according to IEC standards, or as appropriate. SPSR [1:0] = 00: Transmit sample rate is 44.1 kHz. SPSR [1:0] = 01: Reserved. SPSR [1:0] = 10: Transmit sample rate is 48 kHz (reset default). SPSR [1:0] = 11: Not supported. This bit affects the validity flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF transmitter to maintain connection during error or mute conditions. V = 1: Each SPDIF subframe (L + R) has Bit 28 set to 1. This tags both samples as invalid. V = 0: Each SPDIF subframe (L + R) has Bit 28 set to 0 for valid data and 1 for invalid data (error condition). When V = 0, asserting the VFORCE bit (D15) in Register 0x2A (Ext'd Audio Stat/Ctrl) forces the validity flag low, marking both samples as valid.
V
Validity
EQ CONTROL REGISTER
Index 0x60
Reg No. 0x60 Name EQ Ctrl D15 EQM D14 MAD LBEN D13 X D12 X D11 X D10 X D9 X D8 X D7 SYM D6 CHS D5 BCA5 D4 BCA4 D3 BCA3 D2 BCA2 D1 BCA1 D0 BCA0 Default 0x8080
Register 0x60 is a read/write register that controls the equalizer functionality and data setup. This register contains the biquad and coefficient address pointer, which is used in conjunction with the EQ data register (0x78) to set up the equalizer coefficients. The reset default disables the equalizer function until the coefficients can be properly set up by the software and sets the symmetry bit to allow equal coefficients for left and right channels. All registers are not shown, and bits containing an X are assumed to be reserved.
Table 36.
Bit BCA [5:0] Mnemonic Biquad and Coefficient Address Pointer Function biquad 0 coef a0 BCA[5:0] = 011011 biquad 0 coef a1 BCA[5:0] = 011010 biquad 0 coef a2 BCA[5:0] = 011001 biquad 0 coef b1 BCA[5:0] = 011101 biquad 0 coef b2 BCA[5:0] = 011100 biquad 1 coef a0 BCA[5:0] = 100000 biquad 1 coef a1 BCA[5:0] = 011111
Rev. A | Page 24 of 32
AD1981BL
Bit Mnemonic Function biquad 1 coef a2 BCA[5:0] = 011110 biquad 1 coef b1 BCA[5:0] = 100010 biquad 1 coef b2 BCA[5:0] = 100001 biquad 2 coef a0 BCA[5:0] = 100101 biquad 2 coef a1 BCA[5:0] = 100100 biquad 2 coef a2 BCA[5:0] = 100011 biquad 2 coef b1 BCA[5:0] = 100111 biquad 2 coef b2 BCA[5:0] = 100110 biquad 3 coef a0 BCA[5:0] = 101010 biquad 3 coef a1 BCA[5:0] = 101001 biquad 3 coef a2 BCA[5:0] = 101000 biquad 3 coef b1 BCA[5:0] = 101100 biquad 3 coef b2 BCA[5:0] = 101011 biquad 4 coef a0 BCA[5:0] = 101111 biquad 4 coef a1 BCA[5:0] = 101110 biquad 4 coef a2 BCA[5:0] = 101101 biquad 4 coef b1 BCA[5:0] = 110001 biquad 4 coef b2 BCA[5:0] = 110000 biquad 5 coef a0 BCA[5:0] = 110100 biquad 5 coef a1 BCA[5:0] = 110011 biquad 5 coef a2 BCA[5:0] = 110010 biquad 5 coef b1 BCA[5:0] = 110110 biquad 5 coef b2 BCA[5:0] = 110101 biquad 6 coef a0 BCA[5:0] = 111001 biquad 6 coef a1 BCA[5:0] = 111000 biquad 6 coef a2 BCA[5:0] = 110111 biquad 6 coef b1 BCA[5:0] = 111011 biquad 6 coef b2 BCA[5:0] = 111010 CHS = 0 selects the left-channel coefficient's data block. CHS = 1 selects the right-channel coefficient's data block. When set to 1, this bit indicates that the left- and right-channel coefficients are equal. This shortens the coefficients' setup sequence, because only the left-channel coefficients need to be addressed and set up. The right-channel coefficients are fetched from the left-channel memory. Enables mixer ADC data to be summed into the PCM stream. 0 = No loopback allowed (default). 1 = Enable loopback. When set to 1, this bit disables the equalizer function (allows all data to pass through). The reset default sets this bit to 1, disabling the equalizer function until the biquad coefficients can be properly set.
CHS SYM
Channel Select Symmetry
MAD LBEN EQM
Mixer ADC Loopback Enable Equalizer Mute
Rev. A | Page 25 of 32
AD1981BL
EQ DATA REGISTER
Index 0x62
Reg No. 0x62 Name EQ Data D15 CFD15 D14 CFD14 D13 CFD13 D12 CFD12 D11 CFD11 D10 CFD10 D9 CFD9 D8 CFD8 D7 CFD7 D6 CFD6 D5 CFD5 D4 CFD4 D3 CFD3 D2 CFD2 D1 CFD1 D0 CFD0 Default 0x0000
This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed to by the BCA bits in the EQ Cntrl Register (0x60). Data is written to memory only if the EQM bit (Register 0x60, Bit 15) is asserted.
Table 37.
Bit CFD [15:0] Mnemonic Coefficient Data Function The biquad coefficients are fixed-point format values with 16 bits of resolution. The CFD15 bit is the MSB, and the CFD0 bit is the LSB.
MIXER ADC, INPUT GAIN REGISTER
Index 0x64
Reg No. 0x64 Name Mixer ADC, Volume D15 MXM D14 X D13 X D12 X D11 LMG3 D10 LMG2 D9 LMG1 D8 LMG0 D7 RM1 D6 X D5 X D4 X D3 RMG3 D2 RMG2 D1 RMG1 D0 RMG0 Default 0x8000
1
For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 39 for examples.
Table 38.
Bit RMG [3:0] RM LMG [3:0] MXM Mnemonic Right Mixer Gain Control Right-Channel Mute Left Mixer Gain Control Mixer Gain Register Mute Function This register controls the gain into the mixer ADC from 0 dB to a maximum gain of 22.5 dB. The least significant bit represents 1.5 dB. Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the MXM bit. Otherwise, this bit always reads 0 and has no affect when set to 1. This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of 22.5 dB. The least significant bit represents 1.5 dB. 0 = Unmuted. 1 = Muted (reset default).
Table 39. Settings for Mixer ADC, Input Gain
Reg. 0x76 MSPLT1 0 0 0 1 1 1 D15 0 0 1 0 1 1 Control Bits Mixer ADC, Input Gain (0x64) Left-Channel Mixer Gain D [11:8] Right-Channel Mixer Gain D [3:0] Write Readback Function D71 Write Readback Function 1111 1111 22.5 dB Gain X 1111 1111 22.5 dB Gain 0000 0000 0 dB Gain X 0000 0000 0 dB Gain XXXX XXXX - dB Gain, Muted X XXXX XXXX - dB Gain, Muted 1111 1111 22.5 dB Gain 1 XXXX XXXX - dB Gain, Right Only Muted XXXX XXXX - dB Gain, Left Only Muted 0 1111 1111 22.5 dB Gain XXXX XXXX - dB Gain, Left Muted 1 XXXX XXXX - dB Gain, Right Muted
1
For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. X is a wild card, and has no effect on the value.
Rev. A | Page 26 of 32
AD1981BL
JACK SENSE/AUDIO INTERRUPT/STATUS REGISTER
Index 0x72
Reg No. 0x72 Name Jack Sense D15 X D14 X D13 X D12 JS MT2 D11 JS MT1 D10 JS MT0 D9 JS1 EQB D8 JS0 EQB D7 JS1 TMR D6 JS0 TMR D5 JS1 MD D4 JS0 MD D3 JS1 ST D2 JS0 ST D1 JS1 INT D0 JS0 INT Default 0x0000
All register bits are read/write except for JS0ST and JS1ST, which are read-only. All registers are not shown, and bits containing an X are assumed to be reserved.
Table 40.
Bit JS0INT Mnemonic JS0 Interrupt Function This bit indicates that Pin JS0 has generated an interrupt. This bit remains set until the software services the JS0 interrupt, that is, JS0 ISR should clear this bit by writing a 0 to it. The interrupt to the system is an OR combination of this bit and JS1INT. The actual interrupt implementation is selected by the INTS bit (Register 0x76). It is also possible to generate a software system interrupt by writing a 1 to this bit. This bit indicates that Pin JS1 has generated an interrupt. This bit remains set until the software services the JS1 interrupt, that is, JS1 ISR should clear this bit by writing a 0 to it. See the JS0INT description for details. This bit always reports the logic state of the JS0 pin. This bit always reports the logic state of the JS1 pin. This bit selects the operation mode for the JS0 pin. 0 = Jack sense mode (default). 1 = Interrupt mode. This bit selects the operation mode for the JS1 pin. 0 = Jack sense mode (default). 1 = Interrupt mode. If this bit is set to 1, JS0 must be high for >278 ms to be recognized. If this bit is set to 1, JS1 must be high for >278 ms to be recognized. This bit enables JS0 to control the EQ bypass. When this bit is set to 1, JS0 = 1 causes the EQ to be bypassed. This bit enables JS1 to control the EQ bypass. When this bit is set to 1, JS1 = 1 causes the EQ to be bypassed. These three bits select and enable the jack sense muting action (see Table 41).
JS1INT
JS1 Interrupt
JS0ST JS1ST JS0MD
JS0 State JS1 State JS0 Mode
JS1MD
JS1 Mode
JS0TMR JS1TMR JS0EQB JS1EQB JSMT [2:0]
JS0 Timer Enable JS1 Timer Enable JS0 EQ Bypass Enable JS1 EQ Bypass Enable JS Mute Enable Selector
Rev. A | Page 27 of 32
AD1981BL
Table 41. Jack Sense Mute Select--JSMT [2:0]
Ref 0 1 2 3 4 5 6 7 8 JS1 Headphone OUT (0) OUT (0) IN (1) IN (1) OUT (0) OUT (0) IN (1) IN (1) OUT (0) JS0 LINE_OUT OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) JSMT2 0 0 0 0 0 0 0 0 0 JSMT1 0 0 0 0 0 0 0 0 1 JSMT0 0 0 0 0 1 1 1 1 0 HP_OUT ACTIVE ACTIVE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE FMUTE LINE_OUT ACTIVE ACTIVE ACTIVE ACTIVE FMUTE ACTIVE FMUTE FMUTE FMUTE MONO_OUT ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Notes JS0 and JS1 ignored.
JS0 no mute action; JS1 mutes Line_Out.
JS0 no mute action; JS1 mutes Mono and Line-Out.
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
OUT (0) IN (1) IN (1) OUT (0) OUT (0) IN (1) IN (1) OUT (0) OUT (0) IN (1) IN (1) OUT (0) OUT (0) IN (1) IN (1) OUT (0)
IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0)
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
FMUTE ACTIVE ACTIVE ** ** ** ** FMUTE FMUTE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE FMUTE
ACTIVE FMUTE FMUTE ** ** ** ** FMUTE ACTIVE FMUTE ACTIVE FMUTE ACTIVE FMUTE FMUTE FMUTE
ACTIVE FMUTE FMUTE ** ** ** ** ACTIVE FMUTE ACTIVE FMUTE ACTIVE FMUTE ACTIVE FMUTE ACTIVE
** Reserved.
JS0 mutes Mono; JS1 no mute action.
JS0 mutes Mono; JS1 mutes Line-Out.
JS0 mutes Mono; JS1 mutes Mono and Line-Out.
25 26 27 28 29 30 31
OUT (0) IN (1) IN (1) OUT (0) OUT (0) IN (1) IN (1)
IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1)
1 1 1 1 1 1 1
1 1 1 1 1 1 1
0 0 0 1 1 1 1
FMUTE ACTIVE ACTIVE ** ** ** **
ACTIVE FMUTE FMUTE ** ** ** **
FMUTE FMUTE FMUTE ** ** ** **
** Reserved.
FMUTE = Output is forced to mute independent of the respective volume register setting. ACTIVE = Output is not muted, and its status is dependent on the respective volume register setting. OUT = Nothing plugged into the jack and, therefore, the JS status is low (via the load resistor pull-down). IN = Jack has plug inserted and, therefore, the JS status is high (via the codec JS internal pull-up).
Rev. A | Page 28 of 32
AD1981BL
SERIAL CONFIGURATION REGISTER
Index 0x74
Reg No. 0x74 Name Serial Config D15 SLOT16 D14 REGM2 D13 REGM1 D12 REGM0 D11 X D10 X D9 X D8 CHEN D7 X D6 X D5 X D4 INTS D3 X D2 SPAL D1 SPDZ D0 SPLNK Default 0x7001
This register is not reset when the reset register (Register 0x00) is written. All registers are not shown, and bits containing an X are assumed to be reserved.
Table 42.
Bit SPLNK Mnemonic SPDIF Link Function This bit enables the SPDIF to link with the DAC for data requests. 0 = SPDIF and DAC are not linked. 1 = SPDIF and DAC are linked and receive the same data requests (reset default). 0 = Repeat last sample out of the SPDIF stream if FIFO underruns (reset default). 1 = Forces midscale sample out the SPDIF stream if FIFO underruns. 0 = SPDIF transmitter is connected to the ac-link stream (reset default). 1 = SPDIF transmitter is connected to the digital ADC stream, not the ac-link. This bit selects the JS interrupt implementation path. 0 = Bit 0 Slot 12 (modem interrupt). 1 = Slot 6 valid bit (MIC ADC interrupt). This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45). 0 = Disable chaining (reset default). 1 = Enable chaining into ID0 pin.
SPDZ SPAL INTS
SPDIF DACZ SPDIF ADC LoopAround Interrupt Mode Select
CHEN
Chain Enable
REGM0 REGM1 REGM2 SLOT16
Master Codec Register Mask Slave 1 Codec Register Mask Slave 2 Codec Register Mask Enable 16-Bit Slot Mode
Slot 16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a preferred mode for DSP serial port interfacing.
MISCELLANEOUS CONTROL BIT REGISTER
Index 0x76
Reg No. 0x76 Name Misc Control Bit D15 DACZ D14 X D13 MSPLT D12 LODIS D11 DAM D10 X D9 FMXE D8 X D7 MADPD D6 2CMIC D5 X D4 MADST D3 VREFH D2 VREFD D1 MBG1 D0 MBG0 Default 0x0000
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 43.
Bit MBG [1:0] Mnemonic MIC Boost Gain Change Register Function These two bits allow changing the MIC preamp gain from the nominal 20 dB gain. This gain setting takes effect only while Bit D6 (M20) on the MIC volume register (0x0E) is set to 1; otherwise, the MIC boost block has a gain of 0 dB. 00 = 20 dB gain (reset default). 01 = 10 dB gain. 10 = 30 dB gain. 11 = Reserved.
Rev. A | Page 29 of 32
AD1981BL
Bit VREFD Mnemonic VREFOUT Disable Function This bit disables VREFOUT, placing it into high Z out mode. This bit overrides the VREFH bit selection. 0 = VREFOUT pin is driven by the internal reference (reset default). 1 = VREFOUT pin is placed into high Z out mode. 0 = VREFOUT pin is set to 2.25 V output (reset default). 1 = VREFOUT pin is set to 2.25 V output (is set to 3.7 V only if AVDD = 5 V). This bit indicates status of the mixer digitizing ADC (left and right channels). 0 = Mixer ADC not ready. 1 = Mixer ADC ready. This bit enables simultaneous recording from MIC1 and MIC2 inputs for applications that use a stereo microphone array. This register works in conjunction with the MS bit in Register 0x20. 0 = MIC1 or MIC2 (determined by the MS bit) is routed to the record selector's left and right MIC channels, as well as to the mixer (reset default). 1 = MIC1 is routed to the record selector's left MIC channel and MIC2 is routed to the record selector's right MIC channel. In this mode, the MS bit should be set low, and MIC1 can still be enabled into the mixer. This bit controls power-down for mixer digitizing ADC. 0 = Mixer ADC is powered on (default). 1 = Mixer ADC is powered down. This bit controls the front (main) DAC to mixer mute switches. 0 = Front DAC outputs are allowed to sum into the mixer (reset default). 1 = Front DAC outputs are muted into the mixer (blocked). PCM DAC outputs bypass the analog mixer and are sent directly to the codec output. This bit disables the LINE_OUT pins (L/R), placing them into high Z mode so that the assigned output audio jack can be shared for the input function (or other function). 0 = LINE_OUT pins have normal audio drive capability (reset default). 1 = LINE_OUT pins are placed into high Z mode. This bit allows separate mute control bits for the master, headphone, LINE_IN, CD, AUX, and PCM volume control registers as well as for the record gain register. 0 = Both left- and right-channel mutes are controlled by Bit 15 in the respective registers (reset default). 1 = Bit 15 affects only the left-channel mute, and Bit 7 affects only the right-channel mute. This bit determines DAC data fill under starved conditions. 0 = DAC data is repeated when DACs are starved for data (reset default). 1 = DAC is zero-filled when DACs are starved for data.
VREFH MADST
VREFOUT High Mixer ADC Status Bit
2CMIC
2-Channel MIC Select
MADPD
Mixer ADC Power-Down
FMXE
Front DAC into Mixer Enable Digital Audio Mode LINE_OUT Disable
DAM LODIS
MSPLT
Mute Split
DACZ
DAC Zero-Fill
Rev. A | Page 30 of 32
AD1981BL
VENDOR ID REGISTERS
Index 0x7C-0x7E
Reg No. 0x7C Name Vendor ID1 D15 F7 D14 F6 D13 F5 D12 F4 D11 F3 D10 F2 D9 F1 D8 F0 D7 S7 D6 S6 D5 S5 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0 Default 0x4144
S[7:0] This register is ASCII encoded to A. F[7:0] This register is ASCII encoded to D.
Reg No. 0x7E
Name Vendor ID2
D15 T7
D14 T6
D13 T5
D12 T4
D11 T3
D10 T2
D9 T1
D8 T0
D7 REV7
D6 REV6
D5 REV5
D4 REV4
D3 REV3
D2 REV2
D1 REV1
D0 REV0
Default 0x5374
T[7:0] This register is ASCII encoded to S. REV[7:0] Vendor-specific revision number: The AD1981BL assigns 0x74 to this field.
Table 44. Codec ID and External Clock Selection
ID1 1 1 0 0 ID0 1 0 1 0 Codec ID (00) Primary (01) Secondary (00) Primary (00) Primary Codec Clocking Source 24.576 MHz 12.288 MHz 48.000 MHz 14.31818 MHz Local crystal or external into XTL_IN. External into BIT_CLK. External into XTL_IN. External into XTL_IN.
Internally, the ID pins have weak pull-ups and are inverted.
Rev. A | Page 31 of 32
AD1981BL OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60 MAX
48 1
PIN 1
9.00 BSC SQ
37 36
1.45 1.40 1.35
0.15 0.05
TOP VIEW
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
(PINS DOWN)
7.00 BSC SQ
12 13 24
25
SEATING PLANE
VIEW A
0.50 BSC LEAD PITCH
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
0.27 0.22 0.17
Figure 10. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters
ORDERING GUIDE
Model AD1981BLJST AD1981BLJST-REEL AD1981BLJSTZ1 AD1981BLJSTZ-REEL1 Temperature Range 0C to 70C 0C to 70C 0C to 70C 0C to 70C Package Description 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] Package Option ST-48 ST-48 ST-48 ST-48
1
Z = Pb-free part. The AD1981BLJSTZ is a lead-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure tin electroplate. The device is suitable for lead-free applications and can withstand surface-mount soldering at up to 255C (5C). In addition, it is backward compatible with conventional tin-lead soldering processes. This means that the electroplated tin coating can be soldered with tinlead solder pastes at reflow temperatures of 220C to 235C.
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04321-0-1/05(A)
Rev. A | Page 32 of 32

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